Method of manufacturing semiconductor device
US10062571B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2016 |
| Grant date | Aug 28, 2018 |
| Priority date | — |
| Expiry date | Nov 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31138
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device includes forming a feature layer on a substrate, forming a plurality of reference patterns, arranged at a first pitch, on the feature layer, forming an organic liner on a side wall of each of the plurality of reference patterns, forming a plurality of buried patterns on the organic liner, removing the organic liner exposed between the plurality of buried patterns and the plurality of reference patterns, and etching the feature layer by using the plurality of buried patterns and the plurality of reference patterns as etch masks to form a feature pattern. Each of the plurality of buried patterns covers a space between side walls of two adjacent reference patterns among the plurality of reference patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.