Programmable integrated circuit standard cell
US10062709B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2016 |
| Grant date | Aug 28, 2018 |
| Priority date | — |
| Expiry date | Feb 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/988
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A standard cell for use within an integrated circuit can be partially personalized by local wiring. The standard cell can include a set of transistors, each having a fixed size and position within an established standard cell perimeter. The set of transistors can be partially interconnected to a set of local nodes by local wiring. Customization ports can be arranged on a global wiring layer and electrically connected to the set of local nodes. A set of blockage in shapes can be arranged to identify, on a global wiring layer, areas reserved for personalization wiring. Personalization wiring can be configured to complete the personalization of the standard cell by electrically interconnecting, on the global wiring layer, some of the set of customization ports.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.