Inventor · Somers, NY, US

James D. Warnock

66Patents
8h-index
94Co-inventors
81Inventor score

Filing activity: Oct 27, 1992 → Jun 5, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US6901546B2 Enhanced debug scheme for LBIST Physics 31 Expired
US5264387A Method of forming uniformly thin, isolated silicon mesas on an insulating substrate Emerging Cross-Sectional Technologies 20 Expired
US5543731A Dynamic and preset static multiplexer in front of latch circuit for use in static circuits Electricity 18 Expired
US7084462B1 Parallel field effect transistor structure having a body contact Electricity 14 Expired
US8104014B2 Regular local clock buffer placement and latch clustering by iterative optimization Physics 13 Active
US7372305B1 Scannable dynamic logic latch circuit Physics 11 Active
US6922818B2 Method of power consumption reduction in clocked circuits Physics 10 Expired
US7888959B2 Apparatus and method for hardening latches in SOI CMOS devices Electricity 9 Active
US6825695B1 Unified local clock buffer structures Physics 8 Expired
US6744282B1 Latching dynamic logic structure, and integrated circuit including same Electricity 7 Expired
US6718523B2 Reduced pessimism clock gating tests for a timing analysis tool Physics 7 Expired
US7191419B2 Method of timing model abstraction for circuits containing simultaneously switching internal signals Physics 6 Expired
US8914765B2 Power grid generation through modification of an initial power grid based on power grid analysis Physics 6 Active
US7719315B2 Programmable local clock buffer Physics 6 Active
US6822500B1 Methods and apparatus for operating master-slave latches Electricity 5 Expired
US9496447B2 Signal distribution in integrated circuit using optical through silicon via Emerging Cross-Sectional Technologies 4 Active
US7225419B2 Methods for modeling latch transparency Physics 4 Expired
US8117579B2 LSSD compatibility for GSD unified global clock buffers Physics 4 Active
US7165006B2 Scan chain disable function for power saving Physics 3 Expired
US7178075B2 High-speed level sensitive scan design test scheme with pipelined test clocks Physics 3 Expired
US9543935B1 Programmable delay circuit including hybrid fin field effect transistors (finFETs) Electricity 3 Active
US7459950B2 Pulsed local clock buffer (LCB) characterization ring oscillator Electricity 3 Active
US9088279B2 Margin improvement for configurable local clock buffer Electricity 2 Active
US6927615B2 Low skew, power efficient local clock signal generation system Physics 2 Expired
US9552455B2 Method for an efficient modeling of the impact of device-level self-heating on electromigration limited current specifications Physics 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.