Integrated circuits with magnetic tunnel junction memory cells and methods for producing the same
US10062733B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2017 |
| Grant date | Aug 28, 2018 |
| Priority date | — |
| Expiry date | May 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/01
Abstract
Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a memory cell with a memory cell upper surface. A capping layer is formed overlying the memory cell, and a portion of the capping layer is removed to expose the memory cell upper surface. A memory cell etch stop is formed overlying the memory cell upper surface after the portion of the capping layer is removed to expose the memory cell upper surface. The memory cell etch stop is removed from overlying the memory cell upper surface, and an interconnect is formed in electrical communication with the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.