Self-aligned gate hard mask and method forming same
US10062784B1 · kind B1 · utility
24Cited by
12References
20Claims
0Family size
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Key dates
| Filing date | Apr 20, 2017 |
| Grant date | Aug 28, 2018 |
| Priority date | — |
| Expiry date | Apr 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a metal gate in a first inter-layer dielectric, performing a treatment on the metal gate and the first inter-layer dielectric, selectively growing a hard mask on the metal gate without growing the hard mask from the first inter-layer dielectric, depositing a second inter-layer dielectric over the hard mask and the first inter-layer dielectric, planarizing the second inter-layer dielectric and the hard mask, and forming a gate contact plug penetrating through the hard mask to electrically couple to the metal gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.