Apparatuses with an embedded combination logic circuit for high speed operations
US10063240B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 23, 2017 |
| Grant date | Aug 28, 2018 |
| Priority date | — |
| Expiry date | Aug 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a first-in-first-out stage comprising an combination logic circuit, a input ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a push signal to the first-in-first-out stage, and a output ring counter circuit coupled to the first-in-first-out stage and configured to selectively provide a pop signal to the first-in-first-out stage, wherein the first-in-first-out stage is configured to perform calculations on input data with the combination logic circuit to generate output data responsive to receiving the push signal and to provide the output data based on the calculations responsive to receiving the pop signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.