Multi-purpose register pages for read training
US10067718B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2016 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Mar 17, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Dynamic random access memory (DRAM) chips in memory modules include multi-purpose registers (MPRs) having pre-defined data patterns which, when selected, are accessed with read commands and output on data lines for performing read training. The MPRs are accessed by issuing read commands to specific register addresses to request reads from specific MPR locations. In some embodiments, read training for memory modules includes addressing, for a first half of a memory module, a read command to a first register address and performing read training using a first set of bit values received in response to addressing using the first register address. For a second half of the memory module, the same read command is used, but read training is performed using a second set of bit values received in response to addressing using the first register address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.