Speeding up younger store instruction execution after a sync instruction

US10067765B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Susan E. Eisen · Round Rock, US
• Hung Q. Le · Austin, US
• Bryan Lloyd · Vestal, US
• Dung Q. Nguyen · Austin, US
• David Scott Ray · Georgetown, US
• Benjamin W. Stolt · Austin, US
• Shih-Hsiung S. Tung · Austin, US

Key dates

• Filing date: May 14, 2012
• Grant date: Sep 4, 2018
• Expiry date: Mar 28, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/3861
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.