David Scott Ray
32Patents
14h-index
51Co-inventors
84Inventor score
Filing activity: Jan 13, 1989 → Feb 10, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6574712B1 | Software prefetch system and method for predetermining amount of streamed data | Physics | 64 | Expired |
| US6460115B1 | System and method for prefetching data to multiple levels of cache including selectively using a software hint to override a hardware prefetch mechanism | Physics | 56 | Expired |
| US6085291A | System and method for selectively controlling fetching and prefetching of data to a processor | Physics | 46 | Expired |
| US7302527B2 | Systems and methods for executing load instructions that avoid order violations | Physics | 44 | Expired |
| US6446167B1 | Cache prefetching of L2 and L3 | Physics | 39 | Expired |
| US5075840A | Tightly coupled multiprocessor instruction synchronization | Physics | 33 | Expired |
| US6148394A | Apparatus and method for tracking out of order load instructions to avoid data coherency violations in a processor | Physics | 27 | Expired |
| US6915415B2 | Method and apparatus for mapping software prefetch instructions to hardware prefetch logic | Physics | 27 | Expired |
| US5613080A | Multiple execution unit dispatch with instruction shifting between first and second instruction buffers based upon data dependency | Physics | 27 | Expired |
| US6112297A | Apparatus and method for processing misaligned load instructions in a processor supporting out of order execution | Physics | 25 | Expired |
| US6535962B1 | System and method for prefetching data using a hardware prefetch mechanism | Physics | 24 | Expired |
| US5440703A | System and method for saving state information in a multi-execution unit processor when interruptable instructions are identified | Physics | 18 | Expired |
| US6463514B1 | Method to arbitrate for a cache block | Physics | 16 | Expired |
| US6957305B2 | Data streaming mechanism in a microprocessor | Physics | 14 | Expired |
| US6035394A | System for providing high performance speculative processing of complex load/store instructions by generating primitive instructions in the load/store unit and sequencer in parallel | Physics | 12 | Expired |
| US8156287B2 | Adaptive data prefetch | Physics | 5 | Active |
| US7464242B2 | Method of load/store dependencies detection with dynamically changing address length | Physics | 4 | Expired |
| US8082423B2 | Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates | Physics | 4 | Active |
| US7376816B2 | Method and systems for executing load instructions that achieve sequential load consistency | Physics | 4 | Expired |
| US8086801B2 | Loading data to vector renamed register from across multiple cache lines | Physics | 3 | Active |
| US9389867B2 | Speculative finish of instruction execution in a processor core | Physics | 2 | Active |
| US9384002B2 | Speculative finish of instruction execution in a processor core | Physics | 2 | Active |
| US7953960B2 | Method and apparatus for delaying a load miss flush until issuing the dependent instruction | Physics | 1 | Expired |
| US7769985B2 | Load address dependency mechanism system and method in a high frequency, low power processor system | Physics | 1 | Active |
| US7730290B2 | Systems for executing load instructions that achieve sequential load consistency | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.