Aware system, method and computer program product for detecting overlay-related defects in multi-patterned fabricated devices
US10068323B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Oct 11, 2016 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Nov 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A design aware system, method, and computer program product are provided for detecting overlay-related defects in multi-patterned fabricated devices. In use, a design of a multi-patterned fabricated device is received by a computer system. Then, the computer system automatically determines from the design one or more areas of the design that are prone to causing overlay errors. Further, an indication of the determined one or more areas is output by the computer system to an inspection system for use in inspecting a multi-patterned device fabricated in accordance with the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.