Dual mode memory array security apparatus, systems and methods
US10068631B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2015 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Jan 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Read-only (“RO”) data consisting of a physically unclonable function (“PUF”) pattern is written to a ferroelectric random-access memory (“FRAM”) memory array. The FRAM array is baked to imprint the PUF pattern with a selected average depth of imprint and a corresponding average read reliability. The average depth of imprint and corresponding average read reliability are determined during testing after baking. The PUF pattern as read after baking is compared to the PUF pattern as written prior to baking. Additional PUF pattern writing and baking cycles may be performed until the average depth of imprint and associated read reliability reach a first selected level. Integrated circuits determined to be over-imprinted by exceeding a second selected level may be rejected. The first and second levels of PUF pattern imprint are selected such as to produce FRAM arrays with a unique fingerprint for each individual FRAM array-containing integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.