Clive Bittlestone
37Patents
9h-index
42Co-inventors
75Inventor score
Filing activity: Dec 9, 1992 → Jan 25, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5430408A | Transmission gate circuit | Electricity | 68 | Expired |
| US7895551B2 | Generation of standard cell library components with increased signal routing resources | Physics | 60 | Active |
| US5612632A | High speed flip-flop for gate array | Electricity | 47 | Expired |
| US5250852A | Circuitry and method for latching a logic state | Electricity | 45 | Expired |
| US6308307A | Method for power routing and distribution in an integrated circuit with multiple interconnect layers | Electricity | 40 | Expired |
| US6581201B2 | Method for power routing and distribution in an integrated circuit with multiple interconnect layers | Electricity | 26 | Expired |
| US7564077B2 | Performance and area scalable cell architecture technology | Electricity | 13 | Active |
| US9401196B1 | Dual mode ferroelectric random access memory (FRAM) cell apparatus and methods with imprinted read-only (RO) data | Physics | 12 | Active |
| US5381455A | Interleaved shift register | Physics | 10 | Expired |
| US9934411B2 | Apparatus for physically unclonable function (PUF) for a memory array | Emerging Cross-Sectional Technologies | 9 | Active |
| US6909301B2 | Oscillation based access time measurement | Physics | 7 | Expired |
| US8051398B2 | Test method and system for characterizing and/or refining an IC design cycle | Physics | 7 | Active |
| US6380593B1 | Automated well-tie and substrate contact insertion methodology | Electricity | 7 | Expired |
| US6781411B2 | Flip flop with reduced leakage current | Electricity | 7 | Expired |
| US10508937B2 | Ultrasonic flow meter | Electricity | 5 | Active |
| US10152613B2 | Apparatus and method for physically unclonable function (PUF) for a memory array | Emerging Cross-Sectional Technologies | 3 | Active |
| US6771118B2 | System and method for reducing a leakage current associated with an integrated circuit | Physics | 3 | Expired |
| US10068631B2 | Dual mode memory array security apparatus, systems and methods | Electricity | 3 | Active |
| US10108365B1 | Bitflip security attack protection | Physics | 3 | Active |
| US9690517B2 | Dual-mode error-correction code/write-once memory codec | Electricity | 2 | Active |
| US6734743B2 | Oscillation based cycle time measurement | Physics | 2 | Expired |
| US8102187B2 | Localized calibration of programmable digital logic cells | Physics | 2 | Active |
| US7973557B2 | IC having programmable digital logic cells | Electricity | 2 | Active |
| US9772899B2 | Error correction code management of write-once memory codes | Electricity | 1 | Active |
| US10592333B2 | Dual-mode error-correction code/write-once memory codec | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.