Methods, apparatus, and system for global healing of write-limited die through bias temperature instability
US10068660B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2017 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Jun 6, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
We disclose methods, apparatus, and systems for improving semiconductor device writeability through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS through the array VCS driver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.