Methods and apparatus for preventing counter-doping during high temperature processing
US10068769B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Dec 14, 2016 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Dec 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/324
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a described example method, semiconductor wafer with a backside silicon nitride layer is encapsulated with a diffusion barrier layer prior to a high temperature anneal greater than about 1000 degrees Celsius. After the high temperature anneal the diffusion barrier layer and the backside silicon nitride layers are stripped.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.