Methods for preparing layered semiconductor structures
US10068795B2 · kind B2 · utility
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13References
24Claims
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Assignee
Inventors
Key dates
| Filing date | Jan 9, 2015 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Jan 9, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/83893
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for preparing layered semiconductor structures are disclosed. The methods may involve pretreating an ion-implanted donor wafer by annealing the ion-implanted donor wafer to cause a portion of the ions to out-diffuse prior to wafer bonding. The donor structure may be bonded to a handle structure and cleaved without re-implanting ions into the donor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.