Electrical interconnect for an integrated circuit package and method of making same
US10068840B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2017 |
| Grant date | Sep 4, 2018 |
| Priority date | — |
| Expiry date | Jun 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electrical interconnect assembly for use in an integrated circuit package includes a mounting substrate having a thickness defined between a first surface and a second surface thereof and at least one electrically conductive pad formed on the first surface of the mounting substrate. A metallization layer coats a surface of the at least one electrically conductive pad and is electrically coupled thereto. The metallization layer also coats portion of the first surface of the mounting substrate and extends through at least one via formed through the thickness of the mounting substrate. A method of manufacturing an electrical interconnect assembly includes forming at least one top side contact pad on a top surface of a mounting substrate and depositing a metallization layer on the top side contact pad(s), on an exposed portion of the top surface, and into via(s) formed through a thickness of the mounting substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.