Interface circuits configured to interface with multi-rank memory
US10073619B2 · kind B2 · utility
4Cited by
10References
20Claims
0Family size
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Key dates
| Filing date | Dec 14, 2017 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | Dec 14, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.