Multiple endianness compatibility
US10073635B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2015 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | Mar 16, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4013
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples of the present disclosure provide apparatuses and methods for multiple endianness compatibility. An example method comprises receiving a plurality of bytes and determining a particular endianness format of the plurality of bytes. The method can include, responsive to determining the particular endianness format is a first endianness format, reordering bits of each byte of the plurality of bytes on a bytewise basis, storing the reordered plurality of bytes in an array of memory cells, and adjusting a shift direction associated with performing a number of operations on the plurality of bytes stored in the array. The method can include, responsive to determining the particular endianness format is a second endianness format, storing the plurality of bytes in the array without reordering bits of the plurality of bytes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.