System, method and computer-accessible medium for fault analysis driven selection of logic gates to be camouflaged
US10073728B2 · kind B2 · utility
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21Claims
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Key dates
| Filing date | Sep 10, 2014 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | Dec 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Exemplary systems, methods and computer-accessible mediums can be provided that can, for example, determine a camouflaging location(s) of the logic gate(s) using a fault analysis procedure, and can camouflage the logic gate(s) at the location(s) based on the determination. The camouflaging procedure can be performed by replacing the logic gate(s) at the camouflaging location(s) with a further camouflaged gate, which can have a dummy contact(s) or a vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.