System and method for in-memory computing
US10073733B1 · kind B1 · utility
40Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2017 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | Sep 1, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory capable of carrying out compute-in-memory (CiM) operations is disclosed. The memory includes a matrix of bit cells having a plurality of bit cells along one or more rows and a plurality of bit cells along one or more columns, each bit cell having a value stored therein, an address decoder configured to receive addresses and activate two or more of the rows associated with the addresses, and a sensing circuit coupled to each column of bit cells, and configured to provide two or more outputs, wherein each output is associated with at least one compute operation performed on values stored in the bit cells in the column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.