Anand Raghunathan
35Patents
15h-index
44Co-inventors
81Inventor score
Filing activity: Sep 18, 1995 → Jan 30, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6745160B1 | Verification of scheduling in the presence of loops using uninterpreted symbolic simulation | Physics | 65 | Expired |
| US7383166B2 | Verification of scheduling in the presence of loops using uninterpreted symbolic simulation | Physics | 57 | Expired |
| US6163876A | Method for verification of RTL generated from scheduled behavior in a high-level synthesis flow | Physics | 57 | Expired |
| US6105139A | Controller-based power management for low-power sequential circuits | Physics | 51 | Expired |
| US6195786A | Constrained register sharing technique for low power VLSI design | Physics | 40 | Expired |
| US10073733B1 | System and method for in-memory computing | Physics | 40 | Active |
| US6324679A | Register transfer level power optimization with emphasis on glitch analysis and reduction | Physics | 36 | Expired |
| US7134100B2 | Method and apparatus for efficient register-transfer level (RTL) power estimation | Physics | 36 | Expired |
| US8286172B2 | Systems and methods for implementing best-effort parallel computing frameworks | Physics | 32 | Active |
| US7278123B2 | System-level test architecture for delivery of compressed tests | Physics | 29 | Expired |
| US5831864A | Design tools for high-level synthesis of a low-power data path | Physics | 24 | Expired |
| US6735744B2 | Power mode based macro-models for power estimation of electronic circuits | Physics | 22 | Expired |
| US5726996A | Process for dynamic composition and test cycles reduction | Physics | 21 | Expired |
| US6877053B2 | High performance communication architecture for circuit designs using probabilistic allocation of resources | Physics | 16 | Expired |
| US6308313A | Method for synthesis of common-case optimized circuits to improve performance and power dissipation | Physics | 15 | Expired |
| US6275969A | Common case optimized circuit structure for high-performance and low-power VLSI designs | Physics | 10 | Expired |
| US8225074B2 | Methods and systems for managing computations on a hybrid computing platform including a parallel accelerator | Physics | 9 | Active |
| US7173906B2 | Flexible crossbar switching fabric | Electricity | 8 | Expired |
| US9122523B2 | Automatic pipelining framework for heterogeneous parallel computing systems | Physics | 7 | Active |
| US7529669B2 | Voice-based multimodal speaker authentication using adaptive training and applications thereof | Physics | 6 | Active |
| US6625781B2 | Multi-level power macromodeling | Physics | 5 | Expired |
| US6694488B1 | System for the design of high-performance communication architecture for system-on-chips using communication architecture tuners | Physics | 4 | Expired |
| US7260809B2 | Power estimation employing cycle-accurate functional descriptions | Physics | 4 | Expired |
| US10135849B2 | Securing medical devices through wireless monitoring and anomaly detection | Electricity | 4 | Active |
| US8762794B2 | Cross-layer system architecture design | Physics | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.