Memory systems and methods for improved power management
US10074417B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2015 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | Nov 4, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.