Frederick A. Ware
740Patents
43h-index
115Co-inventors
93Inventor score
Filing activity: Oct 22, 1979 → Jun 27, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6889304B2 | Memory device supporting a dynamically configurable core organization | Emerging Cross-Sectional Technologies | 218 | Expired |
| US7043599B1 | Dynamic memory supporting simultaneous refresh and data-access transactions | Physics | 203 | Expired |
| US5390308A | Method and apparatus for address mapping of dynamic random access memory | Physics | 190 | Expired |
| US7269708B2 | Memory controller for non-homogenous memory system | Emerging Cross-Sectional Technologies | 184 | Expired |
| US6675272B2 | Method and apparatus for coordinating memory operations among diversely-located memory components | Physics | 164 | Expired |
| US6075730A | High performance cost optimized memory with delayed memory writes | Physics | 151 | Expired |
| US5337285A | Method and apparatus for power control in devices | Physics | 148 | Expired |
| US5430676A | Dynamic random access memory system | Physics | 146 | Expired |
| US8588280B2 | Asymmetric communication on shared links | Emerging Cross-Sectional Technologies | 141 | Active |
| US6496897B2 | Semiconductor memory device which receives write masking information | Physics | 137 | Expired |
| US6493789B2 | Memory device which receives write masking and automatic precharge information | Physics | 137 | Expired |
| US5446696A | Method and apparatus for implementing refresh in a synchronous DRAM system | Physics | 131 | Expired |
| US6310814A | Rambus DRAM (RDRAM) apparatus and method for performing refresh operations | Physics | 126 | Expired |
| US8649460B2 | Techniques for multi-wire encoding with an embedded clock | Electricity | 115 | Active |
| US6401167B1 | High performance cost optimized memory | Physics | 113 | Expired |
| US8462891B2 | Error detection and offset cancellation during multi-wire communication | Electricity | 110 | Active |
| US6839266B1 | Memory module with offset data lines and bit line swizzle configuration | Physics | 107 | Expired |
| US7660183B2 | Low power memory device | Physics | 98 | Expired |
| US5511024A | Dynamic random access memory system | Physics | 96 | Expired |
| US6343352B1 | Method and apparatus for two step memory write operations | Physics | 94 | Expired |
| US7581078B2 | Memory controller for non-homogeneous memory system | Emerging Cross-Sectional Technologies | 90 | Active |
| US5872996A | Method and apparatus for transmitting memory requests by transmitting portions of count data in adjacent words of a packet | Physics | 77 | Expired |
| US5537573A | Cache system and method for prefetching of data | Physics | 77 | Expired |
| US5499355A | Prefetching into a cache to minimize main memory access time and cache size in a computer system | Physics | 75 | Expired |
| US5764963A | Method and apparatus for performing maskable multiple color block writes | Physics | 73 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.