Three-dimensional semiconductor memory device including slit with lateral surfaces having periodicity

US10074665B2 · kind B2 · utility

Assignee

• TOSHIBA MEMORY CORPORATION · JP

Inventors

• Genki Kawaguchi · Yokkaichi, JP
• Masanori Fujita · Yokohama, JP
• Hideki Inokuma · Yokkaichi, JP
• Osamu Matsuura · Hiroshima, JP
• Takeshi Imamura · Chigasaki, JP
• Hideo Wada · Kanoya, JP
• Makoto Watanabe · Tokyo, JP
• Hajime Kaneko · Kodaira, JP
• Kenichi Fujii · Yokohama, JP
• Takanobu Itoh · Yokkaichi, JP

Key dates

• Filing date: Sep 6, 2016
• Grant date: Sep 11, 2018
• Expiry date: Sep 6, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/10

Abstract

According to one embodiment, it includes a stacked body including N-number of layers (N is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing M-number of layers (M is an integer of 1 or more and (N−2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.