Patent · US Active

Board integrated interconnect

US10074919B1 · kind B1 · utility

0Cited by

27References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Zhen Zhou · Emeryville, US
Daqiao Du · Lake Oswego, US
Anne M. Sepic · Phoenix, US
Kai Xiao · Lo Wu, CN

Key dates

Filing date	Jun 16, 2017
Grant date	Sep 11, 2018
Priority date	—
Expiry date	Jun 16, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH05K2203/162
WIPO fieldAudio-visual technology
WIPO sectorElectrical engineering

Abstract

Embodiments of the present disclosure may relate to a printed circuit board (PCB) that includes a first outer layer and a second outer layer opposite the first outer layer. The PCB may further include a routing layer between the first outer layer and the second outer layer, and an interconnect positioned within the first outer layer and coupled with the routing layer. The interconnect may include a contact within an opening in the first outer layer, wherein the contact is within a plane defined by an outer surface of the first outer layer. The interconnect may further include a plated via directly coupled with the contact and the routing layer. Other embodiments may be described or claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.