Debugging a computing device
US10078568B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2015 |
| Grant date | Sep 18, 2018 |
| Priority date | — |
| Expiry date | Apr 24, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/273
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a host debugger to carry out a debugging flow on a computing device and a debug controller to couple the host debugger to the computing device. The debug controller receives a bit stream from the host debugger, converts the incoming bit stream into a command according to a protocol, determines whether the command is a first-stage read command or a second-stage read command, and issues the first-stage read command to a data path of the computing device. If the command is a second-stage read command, the debug controller causes a reservation register of the debug controller to provide a data value or status indication to the host debugger through the interface. The reservation register contains read data returned by the first-stage read command and, in response to the second-stage read command, provides a status indication when the first-stage read command has not yet returned read data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.