Enforcing data protection in an interconnect
US10078589B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2015 |
| Grant date | Sep 18, 2018 |
| Priority date | — |
| Expiry date | Feb 20, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Interconnect circuitry and a method of operating the interconnect circuitry are provided, where the interconnect circuitry is suitable to couple at least two master devices to a memory, each comprising a local cache. Any access to the memory mediated by the interconnect circuitry is policed by a memory protection controller situated between the interconnect circuitry and the memory. The interconnect circuitry modifies a coherency type associated with a memory transaction received from one of the master devices to a type which ensures that when a modified version of a copy of a transaction target specified by the issuing master device is stored in a local cache of another master device an access to the transaction target in the memory must take place and therefore must be policed by the memory protection controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.