Daniel Sara
12Patents
3h-index
15Co-inventors
49Inventor score
Filing activity: Apr 17, 2014 → Oct 22, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9507716B2 | Coherency checking of invalidate transactions caused by snoop filter eviction in an integrated circuit | Physics | 6 | Active |
| US11314675B2 | Interface circuitry for exchanging information with master, home, and slave nodes using different data transfer protocols | Physics | 5 | Active |
| US9311244B2 | Enforcing ordering of snoop transactions in an interconnect for an integrated circuit | Physics | 3 | Active |
| US10489323B2 | Data processing system for a home node to authorize a master to bypass the home node to directly send data to a slave | Physics | 1 | Active |
| US9928195B2 | Interconnect and method of operation of an interconnect for ordered write observation (OWO) | Physics | 0 | Active |
| US9442878B2 | Parallel snoop and hazard checking with interconnect circuitry | Physics | 0 | Active |
| US12399735B2 | Managing transaction request identifiers and indicators to control or bypass in-order handling of transaction requests | Physics | 0 | Active |
| US9892072B2 | Transaction response modification within interconnect circuitry | Physics | 0 | Active |
| US9632955B2 | Reorder buffer permitting parallel processing operations with repair on ordering hazard detection within interconnect circuitry | Physics | 0 | Active |
| US10289587B2 | Switching device using buffering | Emerging Cross-Sectional Technologies | 0 | Active |
| US10078589B2 | Enforcing data protection in an interconnect | Physics | 0 | Active |
| US9852088B2 | Hazard checking control within interconnect circuitry | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.