System and method of distinguishing system management mode entries in a translation address cache of a processor
US10078597B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 3, 2015 |
| Grant date | Sep 18, 2018 |
| Priority date | — |
| Expiry date | Apr 23, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor including a memory that stores a system management mode (SMM) value indicative of whether the processor is in SMM, a translation address cache (TAC) that includes multiple entries for storing address translations, in which each entry includes an SMM identifier, hit logic that compares a lookup address with address translations stored in the TAC for determining a hit, in which the hit logic determines a hit only when a corresponding SMM identifier of an entry matches the SMM value, and entry logic that selects an entry of the TAC for storing a determined address translation and that programs an SMM identifier of the selected entry of the TAC to match the SMM value. The processor may include flush logic that distinguishes SMM entries, and processing logic that commands flushing upon entering and/or exiting SMM. Non-SMM entries may remain in the TAC when entering and exiting SMM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.