SRAM memory bit cell comprising n-TFET and p-TFET
US10079056B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2017 |
| Grant date | Sep 18, 2018 |
| Priority date | — |
| Expiry date | Mar 8, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A SRAM memory bit cell is provided that includes a n-TFET and a p-TFET; a storage node formed by the connection of a first electrode of the n-TFET to a first electrode of the p-TFET (drains or sources); and a control circuit able to apply supply voltages on second electrodes of the n-TFET and p-TFET (sources or drains). The control circuit is configured to provide, during a retention mode, supply and bias voltages reverse biasing the n-TFET and p-TFET in a state wherein a conduction current is obtained by band-to-band tunneling in the n-TFET and p TFET. The control circuit is further configured to provide, during a writing of a bit, supply and bias voltages forward biasing the n-TFET and p-TFET and such that one of the n-TFET and p-TFET is in OFF state and that the other of the n-TFET and p-TFET is in ON state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.