Integrated JFET structure with implanted backgate
US10079294B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2016 |
| Grant date | Sep 18, 2018 |
| Priority date | — |
| Expiry date | Jun 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/126
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device contains a JFET with a channel layer having a first conductivity type in a substrate. The JFET has a back gate having a second, opposite, conductivity type below the channel. The back gate is laterally aligned with the channel layer. The semiconductor device is formed by forming a channel mask over the substrate of the semiconductor device which exposes an area for the channel dopants. The channel dopants are implanted into the substrate in the area exposed by the channel mask while the channel mask is in place. The back gate dopants are implanted into the substrate while the channel mask is in place, so that the implanted channel dopants are laterally aligned with the implanted channel dopants.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.