Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region

US10079314B2 · kind B2 · utility

Assignee

• Cypress Semiconductor Corporation · US

Inventors

• Sagy Levy · Jerusalem, IL
• Frederick B. Jenne · Los Gatos, US
• Krishnaswamy Ramkumar · San Jose, US

Key dates

• Filing date: Mar 25, 2014
• Grant date: Sep 18, 2018
• Expiry date: Mar 25, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/685

Abstract

A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region. A gate stack is disposed above the substrate over the channel region. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.