Semiconductor structure and method for reviewing defects
US10082471B2 · kind B2 · utility
1Cited by
2References
10Claims
0Family size
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Key dates
| Filing date | Jan 2, 2017 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Jan 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/5446
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.