Programmable test structure for characterization of integrated circuit fabrication processes
US10082535B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2016 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Oct 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/00
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test structure includes a dedicated addressing circuit that allows large numbers of test devices to be tested simultaneously and the measurement signals read out serially for different test devices. The test structure may be configured for wafer, die or package-level testing. The test structure may be integrated on a common die with the test devices in a single package, provided on separate die in a common package, separately packaged chips or in the form of a collection of standard die configured as the test structure. If on separate die, the test and addressing circuitry is fabricated from a more mature fabrication process than that being characterized for the devices under test. The processes being characterized may be unqualified whereas the test circuitry may be fabricated with different and more mature or qualified processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.