Memory having a static cache and a dynamic cache
US10083119B2 · kind B2 · utility
6Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2017 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Dec 14, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first portion configured to operate as a static single level cell (SLC) cache and a second portion configured to operate as a dynamic SLC cache when the entire first portion of the memory has data stored therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.