DRAM data path sharing via a segmented global data bus
US10083140B2 · kind B2 · utility
1Cited by
6References
25Claims
0Family size
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Key dates
| Filing date | Dec 18, 2015 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | May 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a memory device and a memory bank comprised of a local data bus, a segmented global data bus coupled to the local data bus, and a section select switch that is configurable to direct a signal from the local data bus to either end of the segmented global data bus. Provided also is a computational device comprising a processor and the memory device and optionally a display. Provided also is a method in which a signal is received from a local data bus, and a section select switch is configured to direct the signal from the local data bus to either end of a segmented global data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.