Inventor · Portland, OR, US

Wei Wu

49Patents
7h-index
86Co-inventors
68Inventor score

Filing activity: Dec 28, 2007 → May 10, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US9043674B2 Error detection and correction apparatus and method Electricity 68 Active
US8640005B2 Method and apparatus for using cache memory in a system that supports a low power state Physics 36 Active
US8138239B2 Polymer thermal interface materials Emerging Cross-Sectional Technologies 14 Active
US10936408B2 Error correction of multiple bit errors per codeword Physics 11 Active
US8533572B2 Error correcting code logic for processor caches that uses a common set of check bits Physics 10 Active
US8762821B2 Method of correcting adjacent errors by using BCH-based error correction coding Electricity 8 Active
US9373395B1 Apparatus to reduce retention failure in complementary resistive memory Physics 7 Active
US11182242B2 Technologies for preserving error correction capability in compute-in-memory operations Physics 6 Active
US9048834B2 Grouping of physically unclonable functions Electricity 6 Active
US9934827B2 DRAM data path sharing via a split local data bus Physics 5 Active
US8245111B2 Performing multi-bit error correction on a cache line Electricity 5 Active
US10001806B2 Computing device with two or more display panels Physics 5 Active
US7941631B2 Providing metadata in a translation lookaside buffer (TLB) Physics 3 Active
US10129036B2 Post-processing mechanism for physically unclonable functions Electricity 3 Active
US9992031B2 Dark bits to reduce physically unclonable function error rates Electricity 2 Active
US9830988B2 Apparatus to reduce retention failure in complementary resistive memory Physics 2 Active
US9934082B2 Apparatus and method for detecting single flip-error in a complementary resistive memory Electricity 2 Active
US10268539B2 Apparatus and method for multi-bit error detection and correction Electricity 2 Active
US10860419B2 Minimal aliasing bit-error correction code Physics 1 Active
US10083140B2 DRAM data path sharing via a segmented global data bus Physics 1 Active
US11023320B2 Technologies for providing multiple levels of error correction Physics 1 Active
US10459809B2 Stacked memory chip device with enhanced data protection capability Electricity 1 Active
US9251095B2 Providing metadata in a translation lookaside buffer (TLB) Physics 1 Active
US11237903B2 Technologies for providing ECC pre-provisioning and handling for cross-point memory and compute operations Physics 1 Active
US8806285B2 Dynamically allocatable memory error mitigation Physics 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.