Adaptive calibration scheduling for a memory subsystem based on calibrations of delay applied to data strobe and calibration of reference voltage
US10083736B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2016 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Jun 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for adaptive calibration scheduling is disclosed. A calibration circuit may perform calibrations of a delay applied to a data strobe conveyed from a memory controller to the memory, and may also calibrate a reference voltage. After calibrating the data strobe delay, a current width of an eye opening and a current score are determined. If the eye opening is not less than a minimum threshold and the current score is within a specified range of a reference score, the reference voltage calibration, if conditionally scheduled, is inhibited. The results of the calibration may be recorded in a history table. A timer may advance a pointer provided to a sequence table at a rate determined by information stored in the history table. Information stored in an entry of the sequence table may indicate which calibration procedures are to be performed during the next calibration cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.