Robert E. Jeter
50Patents
10h-index
51Co-inventors
81Inventor score
Filing activity: Aug 12, 2002 → May 8, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7290096B2 | Full access to memory interfaces via remote request | Electricity | 38 | Expired |
| US7047370B1 | Full access to memory interfaces via remote request | Electricity | 31 | Expired |
| US7290105B1 | Zero overhead resource locks with attributes | Physics | 23 | Expired |
| US7155588B1 | Memory fence with background lock release | Physics | 20 | Expired |
| US7254687B1 | Memory controller that tracks queue operations to detect race conditions | Physics | 20 | Expired |
| US7194568B2 | System and method for dynamic mirror-bank addressing | Physics | 19 | Expired |
| US8041929B2 | Techniques for hardware-assisted multi-threaded processing | Physics | 14 | Active |
| US9666264B1 | Apparatus and method for memory calibration averaging | Physics | 11 | Active |
| US10083736B1 | Adaptive calibration scheduling for a memory subsystem based on calibrations of delay applied to data strobe and calibration of reference voltage | Physics | 10 | Active |
| US9305622B1 | Data strobe to data delay calibration | Electricity | 10 | Active |
| US9990973B1 | Systems and methods using neighboring sample points in memory subsystem calibration | Physics | 9 | Active |
| US9672882B1 | Conditional reference voltage calibration of a memory system in data transmisson | Physics | 7 | Active |
| US10734983B1 | Duty cycle correction with read and write calibration | Physics | 7 | Active |
| US11217285B1 | Memory subsystem calibration using substitute results | Physics | 6 | Active |
| US9286961B1 | Memory controller half-clock delay adjustment | Physics | 5 | Active |
| US10242723B1 | Method and apparatus for background memory subsystem calibration | Emerging Cross-Sectional Technologies | 5 | Active |
| US9640244B1 | Pre-calibration for multiple performance states | Emerging Cross-Sectional Technologies | 5 | Active |
| US9436387B2 | System and method for calibration of a memory interface | Physics | 4 | Active |
| US9698797B1 | Hierarchical feedback-controlled oscillator techniques | Electricity | 4 | Active |
| US9396778B1 | Conditional memory calibration cancellation | Physics | 4 | Active |
| US10408863B2 | Reference voltage prediction in memory subsystem | Emerging Cross-Sectional Technologies | 4 | Active |
| US9477259B2 | Calibration of clock signal for data transmission | Physics | 3 | Active |
| US9691470B1 | Apparatus and method for restricted range memory calibration | Physics | 3 | Active |
| US7257681B2 | Maintaining entity order with gate managers | Electricity | 3 | Expired |
| US11960739B1 | Nominal distance reference voltage calibration | Physics | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.