Three-dimensional three-port bit cell and method of assembling same
US10083739B2 · kind B2 · utility
1Cited by
3References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 18, 2014 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Jul 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-port, three-dimensional bit cell generally comprises a read portion of a cell disposed on a first tier. The read portion comprises a plurality of read port elements. The three-port bit cell further comprises a write portion of the cell disposed on a second tier that is vertically stacked with respect to the first tier. The first and second tiers are coupled using at least one via. The write portion comprises a plurality of write port elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.