Ching-Wei Wu
77Patents
7h-index
63Co-inventors
75Inventor score
Filing activity: Apr 27, 2004 → Feb 16, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6903436B1 | Multiple-time programmable electrical fuse utilizing MOS oxide breakdown | Electricity | 15 | Expired |
| US7502277B2 | Word-line driver design for pseudo two-port memories | Physics | 15 | Active |
| US9281311B2 | Memory cell array including a write-assist circuit and embedded coupling capacitor and method of forming same | Physics | 14 | Active |
| US7952911B2 | SRAM cell array structure | Physics | 10 | Active |
| US9666302B1 | System and method for memory scan design-for-test | Physics | 10 | Active |
| US9455025B2 | Static random access memory and method of controlling the same | Physics | 8 | Active |
| US9001611B1 | Three-dimensional two port register file | Physics | 7 | Active |
| US9490006B2 | Time division multiplexed multiport memory | Electricity | 6 | Active |
| US8395950B2 | Memory device having a clock skew generator | Physics | 6 | Active |
| US7613054B2 | SRAM device with enhanced read/write operations | Electricity | 4 | Active |
| US9230622B2 | Simultaneous two/dual port access on 6T SRAM | Physics | 4 | Active |
| US8406058B2 | Read only memory and operating method thereof | Physics | 3 | Active |
| US8437210B2 | Asymmetric sense amplifier design | Physics | 3 | Active |
| US10937477B1 | Shared decoder circuit and method | Physics | 3 | Active |
| US11190169B2 | Latch circuit, memory device and method | Physics | 2 | Active |
| US9851915B2 | Two-stage read/write 3D architecture for memory devices | Electricity | 2 | Active |
| US11042688B1 | Method of certifying safety levels of semiconductor memories in integrated circuits | Physics | 2 | Active |
| US11289141B2 | Integrated circuit with asymmetric arrangements of memory arrays | Physics | 2 | Active |
| US8411479B2 | Memory circuits, systems, and methods for routing the memory circuits | Electricity | 1 | Active |
| US10083739B2 | Three-dimensional three-port bit cell and method of assembling same | Electricity | 1 | Active |
| US9245615B2 | Boost system for dual-port SRAM | Physics | 1 | Active |
| US8565009B2 | Access to multi-port devices | Physics | 1 | Active |
| US8845247B2 | Thermal compensation system for a milling machine | Emerging Cross-Sectional Technologies | 1 | Active |
| US8837192B2 | N-bit rom cell | Physics | 1 | Active |
| US11811404B2 | Latch circuit, memory device and method | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.