Package stiffener for protecting semiconductor die
US10083920B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2018 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Feb 1, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/49811
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The subject matter of this specification generally relates to electronic packages. In some implementations, a lidless electronic package includes a substrate having a surface and a die disposed on the surface of the substrate. The die has an outside perimeter, a bottom surface adjacent to the surface of the substrate, and a top surface. The electronic package includes a stiffener disposed on the surface of the substrate. The stiffener includes a first surface that is a first distance from the surface of the substrate and a second surface disposed between the die and the first surface. The first distance is greater than a distance between the surface of the substrate and the top surface of the die. The second surface is a second distance from the surface of the substrate that is less than the distance between the surface of the substrate and the top surface of the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.