Chip package structure with bump
US10083927B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2017 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Dec 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package structure is provided. The chip package structure includes a redistribution substrate. The chip package structure includes a first chip structure over the redistribution substrate. The chip package structure includes a first solder bump arranged between and electrically connecting the redistribution substrate and the first chip structure. The chip package structure includes a first molding layer surrounding the first chip structure. The first molding layer and the first chip structure are both spaced apart from the redistribution substrate by the first solder bump, thereby defining a gap there-between. The chip package structure includes a second chip structure over the first chip structure. The chip package structure includes a second molding layer surrounding the second chip structure. The chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump, and filled into the gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.