Semiconductor device reducing parasitic loop inductance of system
US10083930B2 · kind B2 · utility
1Cited by
2References
13Claims
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Key dates
| Filing date | Jan 20, 2017 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Jan 25, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device reducing parasitic loop inductance of system for the switching converter. The semiconductor device has an input voltage pin, a ground reference pin, a switching pin, and a semiconductor die, wherein the semiconductor die comprises a high-side power switch and a low-side power switch and a metal connection. The metal connection directly connects the high-side power switch and the first terminal of the low-side power switch, and is along and proximity to an edge of the semiconductor device to which the input voltage pin is distributed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.