SERDES built-in sinusoidal jitter injection
US10084591B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2017 |
| Grant date | Sep 25, 2018 |
| Priority date | — |
| Expiry date | Mar 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Embodiments enable built-in sinusoidal jitter injection, for example, in a serializer/deserializer (SERDES) circuit. For example, embodiments can receive a tracking profile that corresponds to a predetermined sinusoidal jitter (SJ) profile and a predetermined phase interpolator (PI) profile. A shift determination can be made for each of a plurality of insertion times according to the tracking profile, the shift determination indicating whether to adjust phase interpolation of the SERDES circuit. At each of the plurality of insertion times, a phase adjustment signal can be generated as a function of the shift determination. For example, the phase adjustment signal can indicate a control code for a phase interpolator coupled to a clock generator of the SERDES, and the signal can be output to the phase interpolator. Some implementations adjust the phase interpolator in response to the phase adjustment signal, such that the phase interpolator injects SJ that substantially tracks the SJ profile.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.