Inventor · San Jose, CA, US

Pradeep Nagarajan

14Patents

6h-index

14Co-inventors

59Inventor score

Filing activity: Oct 8, 2008 → Jun 24, 2019

Most-cited inventions

Patent	Title	Area	Cited by	Status
US9711189B1	On-die input reference voltage with self-calibrating duty cycle correction	Physics	32	Active
US8565034B1	Variation compensation circuitry for memory interface	Physics	19	Active
US8237475B1	Techniques for generating PVT compensated phase offset to improve accuracy of a locked loop	Electricity	10	Active
US10084591B1	SERDES built-in sinusoidal jitter injection	Electricity	9	Active
US7893739B1	Techniques for providing multiple delay paths in a delay circuit	Electricity	7	Active
US8624647B2	Duty cycle correction circuit for memory interfaces in integrated circuits	Electricity	7	Active
US8130016B2	Techniques for providing reduced duty cycle distortion	Electricity	6	Active
US8787097B1	Circuit design technique for DQS enable/disable calibration	Physics	6	Active
US8847626B1	Circuits and methods for providing clock signals	Electricity	4	Active
US8680905B1	Digital PVT compensation for delay chain	Physics	3	Active
US9158873B1	Circuit design technique for DQS enable/disable calibration	Physics	3	Active
US11138126B2	Testing hierarchical address translation with context switching and overwritten table definition data	Physics	3	Active
US9059716B1	Digital PVT compensation for delay chain	Physics	1	Active
US8159277B1	Techniques for providing multiple delay paths in a delay circuit	Electricity	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.