Multi-bank memory with multiple read ports and multiple write ports per cycle
US10089018B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2016 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Jun 19, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for data storage includes receiving one or more read commands and one or more write commands, for execution in a same clock cycle in a memory array that comprises multiple single-port memory banks divided into groups. The write commands provide data for storage but do not specify storage locations in which the data is to be stored. One or more of the groups, which are not accessed by the read commands in the same clock cycle, are selected. Available storage locations are chosen for the write commands in the single-port memory banks of the selected one or more groups. During the same clock cycle, the data provided in the write commands is stored in the chosen storage locations, and the data requested by the read commands is retrieved. Execution of the write commands is acknowledged by reporting the chosen storage locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.