Rami Zemach
49Patents
6h-index
57Co-inventors
72Inventor score
Filing activity: Dec 13, 1999 → Apr 15, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6507899B1 | Interface for a memory unit | Physics | 33 | Expired |
| US9876719B2 | Method and apparatus for load balancing in network switches | Electricity | 26 | Active |
| US10601713B1 | Methods and network device for performing cut-through | Electricity | 24 | Active |
| US7304999B2 | Methods and apparatus for processing packets including distributing packets across multiple packet processing engines and gathering the processed packets from the processing engines | Electricity | 17 | Expired |
| US9467399B2 | Processing concurrency in a network device | Physics | 8 | Active |
| US7404015B2 | Methods and apparatus for processing packets including accessing one or more resources shared among processing engines | Electricity | 8 | Expired |
| US9374303B1 | Method and apparatus for processing multicast packets | Electricity | 6 | Active |
| US10200313B2 | Packet descriptor storage in packet memory with cache | Electricity | 6 | Active |
| US10541947B2 | Egress flow mirroring in a network device | Electricity | 5 | Active |
| US10904150B1 | Distributed dynamic load balancing in network systems | Electricity | 5 | Active |
| US9571380B2 | Multi-stage interconnect network in a parallel processing network device | Electricity | 5 | Active |
| US10491718B2 | Method and apparatus for processing packets in a network device | Electricity | 5 | Active |
| US7606250B2 | Assigning resources to items such as processing contexts for processing packets | Electricity | 4 | Active |
| US10411983B2 | Latency monitoring for network devices | Electricity | 4 | Active |
| US9923813B2 | Increasing packet processing rate in a network device | Electricity | 4 | Active |
| US7565496B2 | Sharing memory among multiple information channels | Electricity | 2 | Expired |
| US10089018B2 | Multi-bank memory with multiple read ports and multiple write ports per cycle | Emerging Cross-Sectional Technologies | 2 | Active |
| US10387322B2 | Multiple read and write port memory | Physics | 2 | Active |
| US9461939B2 | Processing concurrency in a network device | Physics | 2 | Active |
| US8972828B1 | High speed interconnect protocol and method | Electricity | 2 | Active |
| US9898431B1 | Method and apparatus for memory access | Physics | 2 | Active |
| US9865503B2 | Method to produce a semiconductor wafer for versatile products | Electricity | 2 | Active |
| US11483244B2 | Packet buffer spill-over in network devices | Electricity | 1 | Active |
| US11075859B2 | Egress packet processing using a modified packet header separate from a stored payload | Electricity | 1 | Active |
| US11962505B1 | Distributed dynamic load balancing in network systems | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.