Memory system architecture
US10089239B2 · kind B2 · utility
1Cited by
1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 26, 2016 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | May 26, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/68
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are methods, systems, and apparatus for managing and controlling memory caches, in particular, system level caches outside of those closest to the CPU. The processes and representative hardware structures that implement the processes are designed to allow for detailed control over the behavior of such system level caches. Caching policies are developed based on policy identifiers, where a policy identifier corresponds to a collection of parameters that control the behavior of a set of cache management structures. For a given cache, one policy identifier is stored in each line of the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.