Shinye Shiu
29Patents
4h-index
24Co-inventors
55Inventor score
Filing activity: Jan 16, 2009 → Nov 21, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8134874B2 | Dynamic leakage control for memory arrays | Physics | 10 | Active |
| US8559247B2 | Dynamic level shifter for interfacing signals referenced to different power supply domains | Physics | 9 | Active |
| US9740631B2 | Hardware-assisted memory compression management using page filter and system MMU | Emerging Cross-Sectional Technologies | 7 | Active |
| US8912853B2 | Dynamic level shifter circuit and ring oscillator using the same | Electricity | 5 | Active |
| US9201796B2 | System cache with speculative read engine | Emerging Cross-Sectional Technologies | 4 | Active |
| US8886886B2 | System cache with sticky removal engine | Physics | 4 | Active |
| US9218286B2 | System cache with partial write valid states | Emerging Cross-Sectional Technologies | 4 | Active |
| US9158685B2 | System cache with cache hint control | Emerging Cross-Sectional Technologies | 4 | Active |
| US9864541B2 | Transparent hardware-assisted memory decompression | Emerging Cross-Sectional Technologies | 3 | Active |
| US9261939B2 | Memory power savings in idle display case | Emerging Cross-Sectional Technologies | 3 | Active |
| US9311251B2 | System cache with sticky allocation | Emerging Cross-Sectional Technologies | 2 | Active |
| US8977817B2 | System cache with fine grain power management | Emerging Cross-Sectional Technologies | 2 | Active |
| US9785571B2 | Methods and systems for memory de-duplication | Emerging Cross-Sectional Technologies | 2 | Active |
| US9396122B2 | Cache allocation scheme optimized for browsing applications | Emerging Cross-Sectional Technologies | 2 | Active |
| US8984227B2 | Advanced coarse-grained cache power management | Emerging Cross-Sectional Technologies | 2 | Active |
| US9280471B2 | Mechanism for sharing private caches in a SoC | Emerging Cross-Sectional Technologies | 2 | Active |
| US8036061B2 | Integrated circuit with multiported memory supercell and data path switching circuitry | Emerging Cross-Sectional Technologies | 2 | Active |
| US10310586B2 | Memory power savings in idle display case | Emerging Cross-Sectional Technologies | 1 | Active |
| US9400544B2 | Advanced fine-grained cache power management | Emerging Cross-Sectional Technologies | 1 | Active |
| US10607977B2 | Integrated DRAM with low-voltage swing I/O | Electricity | 1 | Active |
| US9892054B2 | Method and apparatus for monitoring system performance and dynamically updating memory sub-system settings using software to optimize performance and power consumption | Emerging Cross-Sectional Technologies | 1 | Active |
| US8493811B2 | Memory having asynchronous read with fast read output | Physics | 1 | Active |
| US10089239B2 | Memory system architecture | Physics | 1 | Active |
| US9218040B2 | System cache with coarse grain power management | Physics | 1 | Active |
| US9465740B2 | Coherence processing with pre-kill mechanism to avoid duplicated transaction identifiers | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.